- Posted by Thaumatec
- On 11 October 2018
Embedded devices are Thaumatec’s bread and butter so we’re always super interested in the up-and-coming stars in the embedded hardware space. RISC-V is shaping to be exactly that and this makes us excited. In this blog post, I’ll take on explaining what it is, how it’s destined for greatness and ultimately why we think RISC-V matters.
What’s RISC-V anyway?
When you say embedded you typically think ARM: instruction architecture for platforms spanning from ultra-low power to power horses capable of competing with Intel and AMD’s offerings. ARMs are everywhere from netbooks to mobile devices to toasters, and for a very good reason: they’re proven and by this point very well understood.
Sure, Intel is eyeing every opportunity to jump on the mobile bandwagon but so far their ability to penetrate this market is middling at best. There are other alternatives to ARM – AVR, MIPS, Sparc, OpenRISC or ARC – but they all seem to be pigeon-holed into a single, narrow niche without the widespread appeal of the ARM.
This state of affairs is in part the result of how IP licensing business is structured. With the advent of fabless manufacturers the ability to iterate with proven design – especially given how time-consuming integration process can be – ARM is the safest bet to make. The recipe for success is simple: build a SoC around the ARM ecosystem, ship it to TSMC for fabrication, profit.
There are dozens of shops like these in China alone and they make a steady profit. Note however that hardware is useless without the software and community around it and that is something ARM has in spades. With ARM you get great support from compilers and tools developers. It’s not surprising that it is hard for the newcomer to negotiate this moat.
How is RISC-V different?
But when it comes to the economy of scale of the low-end devices shipping in hundreds of millions the only thing that’s better than understood and inexpensive is free (or at the very least more flexible). Manufacturers of the SoCs for the low-end devices operate on slim margins and are entirely at the mercy of ARMs licensing business. After all, in order to ship ARM-compatible cores, you have to pay for the license up front and on top of that pay royalties for every unit manufactured.
This is where RISC-V enters the stage. The effort spearheaded by the University of California, Berkeley sometime around 2010 is already an interesting alternative to the ARM. The idea behind RISC-V is an ambitious one: create an extensible, robust instruction set architecture for people to implement in silicon and release it on a permissible license. It’s not the only project that decided to go this route (J-core effort immediately comes to mind) but it’s the most promising one so far.
With good support from gcc and with LLVM backend in the works, RISC-V can already host both Linux and FreeBSD. Its ISA is extensible and supports everything one would want from a modern, scalable CPU: 32- and 64-bit integer instruction sets (with embedded 16- and 32-bit subsets, as well as 128-bit one, being worked on); support for atomic operations; single- double- and quad-point integers; compressed instruction set and many more. A lot of thought has been put to make RISC-V design sturdy and usable in the entire spectrum of solutions ARM is used for today (and then some).
Remember though that this is architecture specification only. What’s needed are actual realizations of the ISA. Thankfully RISC-V has this covered too. There are about a dozen liberally licensed implementations one can feed FPGA with or base ASIC design on. There are physical devices with RISC-V cores shipping today too in the form of FE310 and U540 cores from SiFive (used in HiFive1 and HiFive Unleashed respectively) or GAP8 from GreenWaves.
Sceptics were quick to point out that SoC is more than just a CPU. Much more. At the very least you need a system bus, memory controller (and memory in general), various I/O hardware components from low- to high-speed (I2C, SPI, GPIO, USB,…), MMU and quite a few other bits and pieces. Once you get there you’ve got a completely open solution.
This end-to-end openness is likely of great importance only to the truly paranoid, people worried that NSA is rummaging through their pony collection using capabilities of the notorious Intel Management Engine. And I’m not dismissing their fears, nothing like that, it’s simply that we all know that Rome wasn’t built in a day.
It turns out, however, that Chennai is the Rome or RISC-V. Indian Institute of Technology Madras undertook a herculean task of building the entire SoC around RISC-V from scratch. SHAKTI Processor of IITM is proudly open source and free of charge thank you very much.
But SHAKTI project is more than just a CPU. It’s ditching AMBA, the de facto standard bus ARM has designed, and is going for Gen-Z instead. It includes open source SSD controller (based on SHAKTI cores of course), 10G and 25G ethernet components as well as many others and comes in many variants, from embedded to server-bound, from trivial to fault tolerant and aerospace-ready. There’s also a Rust-based OS in the works in case one needs a complete, secure environment. And if you want to drop SHAKTI core into an existing design with SRIO or PCIe, they’ve got you covered as well.
It seems that even ARM accidentally validated the viability of RISC-V when its marketing geniuses launched a hit-piece website with “facts” about RISC-V. Swiftly pulled from the Internet it shows that, if nothing else, the needle has been pushed a little. Historically hardware has been all about walled gardens but this is changing before our eyes. We may not achieve perfect hardware openness (not any time soon at least) but perhaps we don’t have to.
With RISC-V maturing further we’ll see more project using it which in turn will lead to a vibrant ecosystem coalescing around it. Both governments and private sector are investing heavily in RISC-V, betting on its success. RISC-V Foundation boasts an impressive set of members including the likes of Google, Nvidia, Samsung and Western Digital among others. The market is hungry for embedded processors with vibrant communities around it. But most critically the appeal of RISC-V doesn’t end there.
We’re really interested in opportunities that are bound to arise from the maturity of RISC-V. It’s no secret that a lot of embedded projects today boil down to integrating well understood, off the shelf solutions. And that’s not a complaint either – there’s a lot of potential for creative output around such projects. But bringing up a new platform is a completely different beast altogether. And one that we all should be excited to tame. Not that long ago open hardware seemed like an unattainable goal with a very high price of admission for those who attempt it. RISC-V lowers this barrier and that’s going to benefit us all the same way open source software did. Good times.
Now. Can you spot where Harry Potter got paraphrased? 🙂